MineCPU: A 5-stage in-order RISC-V CPU with cache and uart
CS202 Computer Organization (SUSTech), 2024
I am currently a full-time undergraduate in the Department of Computer Science and Engineering, Southern University of Science and Technology since 2022.09, supervised by Prof. Fengwei Zhang. My main research interests include System Security, Architecture, especially in RISC-V.
COMPuter And System Security (COMPASS) Lab @ SUSTech
I am exploring Side-Channel Attacks & Mitigations in RISC-V.
- Microarchitecture Security: Are we still safe from the Meltdown & Spectre?
News
- Our CTF team won the winning prize at CryptoCup. 2024.09
- Our project about education and mitigation of GoFetch attack won the first prize at NUS SOC SWS. 2024.07
- Our project about RISC-V CPU got full marks in pre-demo. 2024.05
Experience
- Visiting Student, School of Computing, NUS, instructed by Prof. Norman Hugh Anderson. 2024.6-7
- Bachelor, Southern University of Science and Technology, Computer Science and Technology. 2022.9 - 2026.6
Projects (๐งโ๐ป indicates co-first author)
Services
- Student Assistant at CS109 2023 Spring, SUSTech
Misc
- ๐ด Neovim lover, also likes every cool things related to Linux or so.
- ๐ Used to be Kendo practicer, now fancy on-road cycling.
- ๐ฎ Cloud player of Zenless Zone Zero for its creative music and arts, fan of Persona Series.
- ๐จโ๐ป CTFer and cybersecurity enthusiast who prefer Web, Crypto and Pentest, but no markable award so far.